By Graham Birtwistle, Alan Davis
As the prices of strength and timing develop into more and more tricky to regulate in conventional synchronous platforms, designers are being pressured to examine asynchronous possible choices. according to transformed and elevated papers from the VII Banff better Order Workshop, this quantity examines asynchronous equipment which were utilized in huge circuit layout, starting from preliminary formal specification to extra commonplace finite country desktop dependent keep watch over types. Written through major practitioners within the region, the papers conceal many elements of present perform together with useful layout, silicon compilation, and functions of formal specification. it is also a state of the art survey of asynchronous layout. The ensuing quantity might be useful to somebody drawn to designing right asynchronous circuits which convey excessive functionality or low energy operation.
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Additional info for Asynchronous Digital Circuit Design
In an asynchronous pipeline, there is no clock. Therefore, in principle, each stage may pass data to its neighbor whenever the stage is done and the neighbor is free. Such elastic pipelines promise improved performance: different stages may operate at different speeds, and stages may complete early depending on the actual data. Of course, new overhead may be introduced, since each stage 31 must now tell its neighbor when it is ready. Sutherland introduced an elegant and influential approach to building asynchronous pipelines, which he called micropipelines .
Seitz, System Timing.  T. W. G. Messerschmitt. Automatic synthesis of asynchronous circuits from high-level specifications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(11):1185-1205, November 1989. H. Meng. Synchronization Design for Digital Systems. Kluwer Academic Publishers, Boston, MA, 1991. E. Miller. Switching Theory. Volume II: Sequential Circuits and Machines. John Wiley and Sons, New York, NY, 1965.  R. Milner. Communication and Concurrency.
For example, asynchronous circuits may use redundant logic to eliminate hazards, but redundant logic makes testing more difficult. Initial results on the testing of speed-independent circuits include work by Beerel and Meng  and Martin and Hazewindus . These papers indicate that certain classes of speed-independent circuits are "self-testing" with respect to stuck-at faults, where certain faults will cause the circuit to halt. Beerel and Meng generalized their approach to handle stuck-at faults in timed control circuits .
Asynchronous Digital Circuit Design by Graham Birtwistle, Alan Davis